WELL ISOLATION TRENCHES (WIT) FOR CMOS DEVICES

• Main Authors: HAKEY MARK C, HORAK DAVID V, FURUKAWA TOSHIHARU, TONTI WILLIAM R, KOBURGER CHARLES W.III, MANDELMAN JACK A
• Format: Patent
• Language: English
• Published: 18.10.2007
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

A well isolation trenches for a CMOS device and the method for forming the same. The CMOS device includes (a) a semiconductor substrate, (b) a P well and an N well in the semiconductor substrate, (c) a well isolation region sandwiched between and in direct physical contact with the P well and the N well. The P well comprises a first shallow trench isolation (STI) region, and the N well comprises a second STI region. A bottom surface of the well isolation region is at a lower level than bottom surfaces of the first and second STI regions. When going from top to bottom of the well isolation region, an area of a horizontal cross section of the well isolation region is an essentially continuous function.