RAMPTIME PROPAGATION ON DESIGNS WITH CYCLES
A method and apparatus for calculating ramptime propagation for integrated circuit layout patterns having pins interconnected in an oriented graph in one or more closed loops is described. Ramptime values are calculated for a first set of the pins, which are not connected to a closed loop while leav...
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| Main Authors | , , , |
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| Format | Patent |
| Language | English |
| Published |
04.10.2007
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| Subjects | |
| Online Access | Get full text |
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| Abstract | A method and apparatus for calculating ramptime propagation for integrated circuit layout patterns having pins interconnected in an oriented graph in one or more closed loops is described. Ramptime values are calculated for a first set of the pins, which are not connected to a closed loop while leaving a second set of the pins with unknown ramptime values. One or more closed loops are identified by backtracking from the pins in the second set with unknown ramptime values. A ramptime value for each pin in the one or more closed loops is calculated iteratively. |
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| AbstractList | A method and apparatus for calculating ramptime propagation for integrated circuit layout patterns having pins interconnected in an oriented graph in one or more closed loops is described. Ramptime values are calculated for a first set of the pins, which are not connected to a closed loop while leaving a second set of the pins with unknown ramptime values. One or more closed loops are identified by backtracking from the pins in the second set with unknown ramptime values. A ramptime value for each pin in the one or more closed loops is calculated iteratively. |
| Author | ZOLOTYKH ANDREJ A GALATENKO ALEXEI V GASANOV ELYAR E LYALIN ILYA V |
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| Notes | Application Number: US20070757229 |
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| SubjectTerms | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS |
| Title | RAMPTIME PROPAGATION ON DESIGNS WITH CYCLES |
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