RAMPTIME PROPAGATION ON DESIGNS WITH CYCLES

A method and apparatus for calculating ramptime propagation for integrated circuit layout patterns having pins interconnected in an oriented graph in one or more closed loops is described. Ramptime values are calculated for a first set of the pins, which are not connected to a closed loop while leav...

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Bibliographic Details
Main Authors GASANOV ELYAR E, ZOLOTYKH ANDREJ A, LYALIN ILYA V, GALATENKO ALEXEI V
Format Patent
LanguageEnglish
Published 04.10.2007
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:A method and apparatus for calculating ramptime propagation for integrated circuit layout patterns having pins interconnected in an oriented graph in one or more closed loops is described. Ramptime values are calculated for a first set of the pins, which are not connected to a closed loop while leaving a second set of the pins with unknown ramptime values. One or more closed loops are identified by backtracking from the pins in the second set with unknown ramptime values. A ramptime value for each pin in the one or more closed loops is calculated iteratively.
Bibliography:Application Number: US20070757229