Viterbi pack instruction
A Viterbi pack instruction is disclosed that masks the contents of a first predicate register with a first masking value and masks the contents of a second predicate register with a second masking value. The resulting masked data is written to a destination register. The Viterbi pack instruction may...
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| Main Authors | , |
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| Format | Patent |
| Language | English |
| Published |
27.09.2007
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| Subjects | |
| Online Access | Get full text |
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| Abstract | A Viterbi pack instruction is disclosed that masks the contents of a first predicate register with a first masking value and masks the contents of a second predicate register with a second masking value. The resulting masked data is written to a destination register. The Viterbi pack instruction may be implemented in hardware, firmware, software, or any combination thereof. |
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| AbstractList | A Viterbi pack instruction is disclosed that masks the contents of a first predicate register with a first masking value and masks the contents of a second predicate register with a second masking value. The resulting masked data is written to a destination register. The Viterbi pack instruction may be implemented in hardware, firmware, software, or any combination thereof. |
| Author | ZENG MAO CODRESCU LUCIAN |
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| Notes | Application Number: US20060389443 |
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| Snippet | A Viterbi pack instruction is disclosed that masks the contents of a first predicate register with a first masking value and masks the contents of a second... |
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| SubjectTerms | BASIC ELECTRONIC CIRCUITRY CODE CONVERSION IN GENERAL CODING DECODING DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TOANOTHER ELECTRICITY |
| Title | Viterbi pack instruction |
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