Viterbi pack instruction
A Viterbi pack instruction is disclosed that masks the contents of a first predicate register with a first masking value and masks the contents of a second predicate register with a second masking value. The resulting masked data is written to a destination register. The Viterbi pack instruction may...
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Main Authors | , |
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Format | Patent |
Language | English |
Published |
27.09.2007
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Subjects | |
Online Access | Get full text |
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Summary: | A Viterbi pack instruction is disclosed that masks the contents of a first predicate register with a first masking value and masks the contents of a second predicate register with a second masking value. The resulting masked data is written to a destination register. The Viterbi pack instruction may be implemented in hardware, firmware, software, or any combination thereof. |
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Bibliography: | Application Number: US20060389443 |