Method for accelerating the RC extraction in integrated circuit designs
The present invention provides a system and method for accelerating the resistance and capacitance (RC) extraction process by performing parallel and distributed processing. The method includes the dividing of a given integrated circuit (IC) design into a limited number of non-overlapping tile block...
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Main Authors | , , |
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Format | Patent |
Language | English |
Published |
30.08.2007
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Subjects | |
Online Access | Get full text |
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Summary: | The present invention provides a system and method for accelerating the resistance and capacitance (RC) extraction process by performing parallel and distributed processing. The method includes the dividing of a given integrated circuit (IC) design into a limited number of non-overlapping tile blocks, distributing tile blocks to standard RC extraction tools, and processing all tiles in parallel by these tools. A tile block includes all information for performing accurate RC extraction. Thereafter, resulting parasitic RC information is assembled to form a complete parasitic RC model for the entire IC. |
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Bibliography: | Application Number: US20060500727 |