TEST APPARATUS
A test apparatus that tests a plurality of electronic devices in parallel is provided. The test apparatus includes: a pattern generating section that generates a test pattern provided to the plurality of electronic devices; a plurality of logical comparator circuits arranged corresponding to the plu...
Saved in:
Main Author | |
---|---|
Format | Patent |
Language | English |
Published |
23.08.2007
|
Subjects | |
Online Access | Get full text |
Cover
Loading…
Summary: | A test apparatus that tests a plurality of electronic devices in parallel is provided. The test apparatus includes: a pattern generating section that generates a test pattern provided to the plurality of electronic devices; a plurality of logical comparator circuits arranged corresponding to the plurality of electronic devices that judges Pass/Fail of an output signal for each pin based on the output signal outputted from each pin for the corresponding electronic device and serially outputs fail information for each pin; a serial reading section that serially reads out for each pin the fail information judged by each of the logical comparator circuit; an OR section that calculates for each of the electronic devices the logical sum of the fail information read out by the serial reading section and generates for each of the electronic devices device fail information indicative of Fail when the fail information for any pin indicates Fail; and an AND section that calculates the logical product of the device fail information generated by the OR section and generates total fail information indicative of Fail when all of the device fail information indicates Fail. |
---|---|
Bibliography: | Application Number: US20070681071 |