Methods of Processing Thick ILD Layers Using Spray Coating or Lamination for C4 Wafer Level Thick Metal Integrated Flow

A process flow to make an interconnect structure with one or more thick metal layers under Controlled Collapse Chip Connection (C4) bumps at a die or wafer level. The interconnect structure may be used in a backend interconnect of a microprocessor. The process flow may include forming an inter-layer...

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Bibliographic Details
Main Authors LEE KEVIN J, GEORGE ANNA M, KIM SARAH E, TOWLE STEVEN
Format Patent
LanguageEnglish
Published 16.08.2007
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:A process flow to make an interconnect structure with one or more thick metal layers under Controlled Collapse Chip Connection (C4) bumps at a die or wafer level. The interconnect structure may be used in a backend interconnect of a microprocessor. The process flow may include forming an inter-layer dielectric with spray coating or lamination over a surface with high aspect ratio structures.
Bibliography:Application Number: US20070740246