MULTI-FREQUENCY DEBUG NETWORK FOR A MULTIPROCESSOR ARRAY

A debug network on a multiprocessor array having multiple clock domains includes a backbone communication channel which communicates with information nodes on the channel. The information nodes store and access information about an attached processor. The nodes are also coupled to registers within t...

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Bibliographic Details
Main Authors JONES ANTHONY M, WHITE EDMUND H, WASSON PAUL M
Format Patent
LanguageEnglish
Published 02.08.2007
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:A debug network on a multiprocessor array having multiple clock domains includes a backbone communication channel which communicates with information nodes on the channel. The information nodes store and access information about an attached processor. The nodes are also coupled to registers within the attached processor, which operate at the speed of the processor. A master controller solicits information from the information nodes by sending messages along the backbone. If a message requires interaction with a processor register, the node performs the action by synchronizing to the local processor clock.
Bibliography:Application Number: US20070676206