Method and system for optimizing latency of dynamic memory sizing

Some embodiments of the invention include a system and method for optimizing the latency of dynamic memory sizing. In some embodiments, the operating requirements can reflect amount of memory required to perform commensurate operations. Memory power management logic is used to coordinate memory requ...

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Bibliographic Details
Main Author JAHAGIRDAR SANJEEV
Format Patent
LanguageEnglish
Published 05.07.2007
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:Some embodiments of the invention include a system and method for optimizing the latency of dynamic memory sizing. In some embodiments, the operating requirements can reflect amount of memory required to perform commensurate operations. Memory power management logic is used to coordinate memory requirements with operating requirements. The latency of changes to the memory based on operating requirements is optimized by the method and system. Other embodiments are described.
Bibliography:Application Number: US20050323259