Microcomputer provided with instruction cache memory

In a microcomputer provided with an instruction cache memory, in which a plurality of programs are executed, the execution time of each of the programs is ensured not be long. After dummy execution of high-priority processing in a time zone when a CPU of the microcomputer is in the process of execut...

Full description

Saved in:
Bibliographic Details
Main Author NAKASATO HIROKI
Format Patent
LanguageEnglish
Published 28.06.2007
Subjects
CALCULATING
COMPUTING
CONJOINT CONTROL OF VEHICLE SUB-UNITS OF DIFFERENT TYPE ORDIFFERENT FUNCTION
CONTROL SYSTEMS SPECIALLY ADAPTED FOR HYBRID VEHICLES
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PERFORMING OPERATIONS
PHYSICS
ROAD VEHICLE DRIVE CONTROL SYSTEMS FOR PURPOSES NOT RELATED TOTHE CONTROL OF A PARTICULAR SUB-UNIT
TRANSPORTING
VEHICLES IN GENERAL
Online AccessGet full text

Cover

More Information
Summary:In a microcomputer provided with an instruction cache memory, in which a plurality of programs are executed, the execution time of each of the programs is ensured not be long. After dummy execution of high-priority processing in a time zone when a CPU of the microcomputer is in the process of executing idle processing, a high-priority processing program is stored in the instruction cache memory. The time for executing the high-priority processing afterwards with normal timing can be reduced because the high-priority processing program has already been stored in the instruction cache memory, whereby the hit rate is increased.
Bibliography:Application Number: US20060642636