STRUCTURE AND METHOD FOR MONITORING STRESS-INDUCED DEGRADATION OF CONDUCTIVE INTERCONNECTS

• Main Authors: COWLEY ANDREW P, RATHORE HAZARA S, CLEVENGER LAWRENCE A, AGARWALA BIRENDRA, CHANDA KAUSHIK, FILIPPI RONALD G, SULLIVAN TIMOTHY D, LEE TOM C, MCLAUGHLIN PAUL S, NGUYEN DU B, LI BAOZHEN, GILL JASON P, YANG CHIHAO
• Format: Patent
• Language: English
• Published: 24.05.2007
• Subjects: MEASURING; MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES; PHYSICS; TESTING

A microelectronic element such as a chip or microelectronic wiring substrate is provided which includes a plurality of conductive interconnects for improved resistance to thermal stress. At least some of the conductive interconnects include a metallic plate, a metallic connecting line and an upper metallic via. The metallic connecting line has an upper surface at least substantially level with an upper surface of the metallic plate, an inner end connected to the metallic plate at one of the peripheral edges, and an outer end horizontally displaced from the one peripheral edge. The metallic connecting line has a width much smaller than the width of the one peripheral edge of the metallic plate and has length greater than the width of the one peripheral edge. The upper metallic via has a bottom end in contact with the metallic connecting line at a location that is horizontally displaced from the one peripheral edge by at least about 3 microns (mum).