Thin film transistor array panel and manufacturing method thereof

A method of manufacturing a thin film transistor array panel is provided, which includes: forming a gate line on a substrate; depositing a gate insulating layer and a semiconductor layer in sequence on the gate line; depositing a lower conductive film and an upper conductive film on the semiconducto...

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Main Authors LEE JEONG-YOUNG, JEON SANG-JIN, BAEK BUM-KI, YU SE-HWAN, CHOI KWON-YOUNG, PARK MIN-WOOK, PARK JUNG-JOON, KWAK SANG-KI, LEE HAN-JU
Format Patent
LanguageEnglish
Published 28.12.2006
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Summary:A method of manufacturing a thin film transistor array panel is provided, which includes: forming a gate line on a substrate; depositing a gate insulating layer and a semiconductor layer in sequence on the gate line; depositing a lower conductive film and an upper conductive film on the semiconductor layer; photo-etching the upper conductive film, the lower conductive film, and the semiconductor layer; depositing a passivation layer; photo-etching the passivation layer to expose first and second portions of the upper conductive film; removing the first and the second portions of the upper conductive film to expose first and second portions of the lower conductive film; forming a pixel electrode and a pair of redundant electrodes on the first and the second portions of the lower conductive film, respectively, the redundant electrodes exposing a part of the second portion of the lower conductive film; removing the exposed part of the second portion of the lower conductive film to expose a portion of the semiconductor layer; and forming a columnar spacer on the exposed portion of the semiconductor layer.
Bibliography:Application Number: US20060512805