Wiring pattern formation method, manufacturing method for multi layer wiring substrate, and electronic device

• Main Authors: SAKURADA KAZUAKI, UEHARA NOBORU, SHINTATE TSUYOSHI
• Format: Patent
• Language: English
• Published: 15.06.2006
• Subjects: BASIC ELECTRIC ELEMENTS; CHEMICAL SURFACE TREATMENT; CHEMISTRY; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATIONOR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY IONIMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; COATING MATERIAL WITH METALLIC MATERIAL; COATING METALLIC MATERIAL; DIFFUSION TREATMENT OF METALLIC MATERIAL; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION INGENERAL; METALLURGY; SEMICONDUCTOR DEVICES; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THESURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION

A wiring pattern formation method in which a wiring pattern is formed by arranging, in a region which is demarcated by a partition wall, liquid material which includes an electrically conductive material, including: arranging a resin material around the periphery of a region upon which the wiring pattern is to be formed; imparting liquid affinity to a demarcated region which has been demarcated by the resin material; narrowing down the demarcated region by flowing out the resin material towards and into the demarcated region; and forming the partition wall by curing the resin material.