Method for modeling inductive effects on circuit performance

A method for testing a partially fabricated wafer is provided that comprises the following steps: providing a device under test (DUT) and three reference oscillators overlying a substrate of the wafer; measuring the frequencies of the reference oscillators as influenced by transistor characteristics...

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Bibliographic Details
Main Author SAVITHRI NAGARAJ N
Format Patent
LanguageEnglish
Published 25.05.2006
Subjects
MEASURING
MEASURING ELECTRIC VARIABLES
MEASURING MAGNETIC VARIABLES
PHYSICS
TESTING
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Summary:A method for testing a partially fabricated wafer is provided that comprises the following steps: providing a device under test (DUT) and three reference oscillators overlying a substrate of the wafer; measuring the frequencies of the reference oscillators as influenced by transistor characteristics, intra structure parasitics, resistive, capacitive and inductive parasitics; and isolating the inductive parasitics by the appropriate comparisons between the reference oscillators.
Bibliography:Application Number: US20040994850