Testing of integrated circuits
An integrated circuit with a test interface contains a boundary scan chain with cells ( 14 ) coupled between a test data input (TDI) and output (TDO) in a shift register structure. Each cell ( 14 ) is also coupled between a respective one of the terminals ( 16 ) and the core circuit ( 10 ). A test c...
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Main Authors | , , |
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Format | Patent |
Language | English |
Published |
11.05.2006
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Subjects | |
Online Access | Get full text |
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Summary: | An integrated circuit with a test interface contains a boundary scan chain with cells ( 14 ) coupled between a test data input (TDI) and output (TDO) in a shift register structure. Each cell ( 14 ) is also coupled between a respective one of the terminals ( 16 ) and the core circuit ( 10 ). A test control circuit (TAP_C) supports an instruction to switch the boundary scan chain to a mode in which mode selectable first ones of the cells ( 14 ) transport data serially along the boundary scan chain while selectable second ones of the cells ( 14 ) write or read data that has been or will be transported through the first ones of the cells ( 14 ) in the further mode to or from the terminals ( 16 ) from or to the scan chain. |
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Bibliography: | Application Number: US20050545121 |