Timeout acceleration for globally shared memory transaction tracking table

A method of operating a central cache controller ("CCC") in a first cell of a multiprocessor system comprising multiple cells each including globally shared memory ("GSM"), wherein the first cell is disposed in a first partition and the CCC is connected to a plurality of CPUs of...

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Bibliographic Details
Main Authors CHONG HUAI-TER V, ADKISSON RICHARD W, GREER CHRISTOPHER
Format Patent
LanguageEnglish
Published 23.03.2006
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC COMMUNICATION TECHNIQUE
ELECTRIC DIGITAL DATA PROCESSING
ELECTRICITY
PHYSICS
TRANSMISSION
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Summary:A method of operating a central cache controller ("CCC") in a first cell of a multiprocessor system comprising multiple cells each including globally shared memory ("GSM"), wherein the first cell is disposed in a first partition and the CCC is connected to a plurality of CPUs of the first cell. In one embodiment, the method comprises, responsive to a new transaction request from one of the CPUs, logging the transaction in a transaction table; determining whether an identity marker in a timeout map corresponding to a cell to which the transaction was issued is set; and, responsive to the corresponding identity marker in the timeout map being set, immediately returning a special error to the one of the CPUs that requested the transaction.
Bibliography:Application Number: US20040944524