Contextual memory interface for network processor

A memory subsystem includes multiple different caches configured for different types of data transfer operations between one or more processing units and a main memory. The different caches can include a first general cache configured for general random memory accesses, a software controlled cache u...

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Bibliographic Details
Main Authors ROWETT KEVIN J, SWEEDLER JONATHAN, TRAN HOAI V, JALALI CAVEH, SIKDAR SOMSUBHRA
Format Patent
LanguageEnglish
Published 26.01.2006
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:A memory subsystem includes multiple different caches configured for different types of data transfer operations between one or more processing units and a main memory. The different caches can include a first general cache configured for general random memory accesses, a software controlled cache used for controlling cache operations for different processing devices accessing the same data, and a streaming cache configured for large packet data memory accesses. An arbiter may be used for arbitrating requests by the multiple different caches for accessing the main memory.
Bibliography:Application Number: US20050181117