System and method for verifying signal propagation delays of circuit traces of a PCB layout
A system for verifying signal propagation delays of circuit traces of a printed circuit board (PCB) layout includes a computer ( 1 ). The computer includes: a setting module ( 10 ) for setting a minimum propagation delay and a maximum propagation delay for a trace to be verified, and making a select...
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Main Authors | , |
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Format | Patent |
Language | English |
Published |
13.10.2005
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Edition | 7 |
Subjects | |
Online Access | Get full text |
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Summary: | A system for verifying signal propagation delays of circuit traces of a printed circuit board (PCB) layout includes a computer ( 1 ). The computer includes: a setting module ( 10 ) for setting a minimum propagation delay and a maximum propagation delay for a trace to be verified, and making a selection regarding whether to calculate a propagation delay of a lead wire connected with the trace; a selecting module ( 11 ) for selecting a segment from a segment set of the trace; a calculating module ( 12 ) for calculating a propagation delay of the segment, the trace and the lead wire, and a total propagation delay; and a determining module ( 13 ) for determining whether all segments of the trace have been calculated, and whether the total propagation delay is between the minimum propagation delay and the maximum propagation delay. A related method is also disclosed. |
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Bibliography: | Application Number: US20040977635 |