Static timing model for combinatorial gates having clock signal input

A method of modeling a combinatorial gate which includes providing a data signal input at the combinatorial gate, providing a clock signal input at the combinatorial gate, propagating the clock signal as an output signal when the output of the combinatorial gate corresponds to the clock signal, and...

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Bibliographic Details
Main Authors SUTHERLAND JEANNETTE N, MAINS ROBERT E, AMATANGELO MATTHEW J
Format Patent
LanguageEnglish
Published 11.08.2005
Edition7
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:A method of modeling a combinatorial gate which includes providing a data signal input at the combinatorial gate, providing a clock signal input at the combinatorial gate, propagating the clock signal as an output signal when the output of the combinatorial gate corresponds to the clock signal, and propagating the data signal as an output when the output of the combinatorial gate corresponds to the data signal, the propagating the data signal modeling a near domino function.
Bibliography:Application Number: US20040774990