Substrate for semiconductor package wire bonding method using thereof
Disclosed is a substrate for semiconductor package and a wire bonding method using thereof. The substrate is provided with at least one reference mark on its surface to check a loading position and a shift state of a solder mask. The reference mark is composed of a combination of a reference pattern...
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Main Authors | , , |
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Format | Patent |
Language | English |
Published |
06.01.2005
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Edition | 7 |
Subjects | |
Online Access | Get full text |
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Summary: | Disclosed is a substrate for semiconductor package and a wire bonding method using thereof. The substrate is provided with at least one reference mark on its surface to check a loading position and a shift state of a solder mask. The reference mark is composed of a combination of a reference pattern and a solder mask opening and is positioned in any location on an outer peripheral edge of a die attachment region. The reference mark may take various shapes. A method for checking a solder mask shift using the reference mark includes comparing a design value of the reference pattern and the solder mask opening with the reference pattern and the solder mask opening, which are formed in an actual material. After the solder mask shift is calculated, a wire bonding coordinate is newly constructed in consideration of the solder mask shift. This minimizes the wire bonding error. |
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Bibliography: | Application Number: US20040884082 |