Manipulating data streams in data stream processors
Techniques for performing user-configurable traffic management functions on streams of packets. The functions include multicasting, discard, scheduling, including shaping, and segmentation and reassembly. In the techniques, the functions are not performed directly on the packets of the stream, but i...
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Main Authors | , , , , , |
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Format | Patent |
Language | English |
Published |
23.12.2004
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Edition | 7 |
Subjects | |
Online Access | Get full text |
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Summary: | Techniques for performing user-configurable traffic management functions on streams of packets. The functions include multicasting, discard, scheduling, including shaping, and segmentation and reassembly. In the techniques, the functions are not performed directly on the packets of the stream, but instead on descriptors that represent stored packets. A packet's descriptor includes at least an identifier for the packet and a specifier for a set of traffic management functions to be performed on the descriptor. The user configures a set of traffic management functions for a traffic queue of descriptors. The specifier in the descriptor specifies a set of traffic management functions by specifying a descriptor queue. In multicasting, a descriptor is copied and placed on more than one traffic queue; with regard to discard, when the discard function associated with a traffic queue determines that a packet is to be discarded, the descriptor is placed in a discard traffic queue. Packets represented by descriptors in a discard traffic queue are discarded from the buffer. Output of descriptors from all traffic queues, including discard traffic queues, is scheduled. Scheduling is done using a hierarchy of schedulers. The form of the hierarchy and the scheduling algorithms used by the schedulers in the hierarchy are both user configurable. As disclosed, the techniques are implemented in a traffic management coprocessor integrated circuit. The traffic manager coprocessor is used with a digital communications processor integrated circuit that performs switching functions. The buffers for the packets are in the digital communications processor. Also disclosed are a modified partial packet discard algorithm and a frame based deficit round robin scheduling algorithm. |
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Bibliography: | Application Number: US20040475066 |