Data selection circuit for performance counter

In one embodiment, the invention is directed to a data selection circuit for a general purpose performance counter ("GPPC") connected to a bus carrying debug data. The data selection circuit is connected to receive the debug data and comprises logic for receiving the debug data as a plural...

Full description

Saved in:
Bibliographic Details
Main Authors ADKISSON RICHARD W, JOHNSON TYLER, GOSTIN GARY B
Format Patent
LanguageEnglish
Published 25.11.2004
Edition7
Subjects
Online AccessGet full text

Cover

Loading…
More Information
Summary:In one embodiment, the invention is directed to a data selection circuit for a general purpose performance counter ("GPPC") connected to a bus carrying debug data. The data selection circuit is connected to receive the debug data and comprises logic for receiving the debug data as a plurality of N-bit portions of block-aligned data and outputting a designated one of the N-bit portions; and circuitry for providing to the receiving logic a control signal for designating one of the N-bit portions.
Bibliography:Application Number: US20030635103