Method and apparatus of constructing a hardware architecture for transform functions

A method and apparatus of constructing a hardware architecture for transform functions is disclosed, which uses a single-input-parallel-output method for processing operations. The transform function has operations of multiplication, path-selection, and accumulation to be executed. The fixed-one-inp...

Full description

Saved in:
Bibliographic Details
Main Authors CHEN OSCAL T.C, CHEN HSIN-HUNG, YEH HENGNG ROGER
Format Patent
LanguageEnglish
Published 25.11.2004
Edition7
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
Online AccessGet full text

Cover

More Information
Summary:A method and apparatus of constructing a hardware architecture for transform functions is disclosed, which uses a single-input-parallel-output method for processing operations. The transform function has operations of multiplication, path-selection, and accumulation to be executed. The fixed-one-input multipliers first multiply an input signal by all transform coefficients. Then a path-selection unit determines correct signal paths and delivers product results to the corresponding accumulators for processing accumulation. Finally, multipliers perform the multiplications of the accumulated values and a constant to obtain output signals.
Bibliography:Application Number: US20030692803