BOND PAD SCHEME FOR CU PROCESS

A novel method of forming a bond pad of a semiconductor device and a novel bond pad structure. Two passivation layers are used to form bond pads of a semiconductor device. A portion of the second passivation layer resides between adjacent bond pads, preventing shorting of the bond pads during subseq...

Full description

Saved in:
Bibliographic Details
Main Authors LIN JIUNN-JYI, CAO MIN, TSENG HUANI, CHANG TZONG-SHENG, LEE YU-HUA, LAI CHIA-HUNG, YANG CHIN-TIEN
Format Patent
LanguageEnglish
Published 25.11.2004
Edition7
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
Online AccessGet full text

Cover

More Information
Summary:A novel method of forming a bond pad of a semiconductor device and a novel bond pad structure. Two passivation layers are used to form bond pads of a semiconductor device. A portion of the second passivation layer resides between adjacent bond pads, preventing shorting of the bond pads during subsequent wire bonding processes or flip-chip packaging processes.
Bibliography:Application Number: US20030444229