Automatic clock gating insertion in an IC design

A computer implemented method is provided for deriving gated clock circuitry in an integrated circuit design comprising: identifying sequential elements and associated feedback loops in the design in the design; for one or more identified sequential elements associated feedback loop, producing a fee...

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Bibliographic Details
Main Authors HUANG STEVE C, FAN YONG, CHEN IHAO
Format Patent
LanguageEnglish
Published 11.11.2004
Edition7
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:A computer implemented method is provided for deriving gated clock circuitry in an integrated circuit design comprising: identifying sequential elements and associated feedback loops in the design in the design; for one or more identified sequential elements associated feedback loop, producing a feedback loop signature associated with such sequential element; evaluating the feedback loop signature associated with such sequential element so as to generate associated stimulus logic; breaking at least one feedback loop and removing at least one feedback element associated with such sequential element so as to generate associated load logic; and inserting the generated stimulus logic and the generated load logic in the design to replace the associated feedback loop.
Bibliography:Application Number: US20030435129