Method and relative circuit for incrementing, decrementing or two's complementing a bit string

A method for incrementing, decrementing or two's complementing a first string of bits includes generating an auxiliary string of bits as a function of the first string, and logically combining the auxiliary string with the first string to generate a corresponding output string. A least signific...

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Bibliographic Details
Main Author IACONO DANIELE LO
Format Patent
LanguageEnglish
Published 15.04.2004
Edition7
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:A method for incrementing, decrementing or two's complementing a first string of bits includes generating an auxiliary string of bits as a function of the first string, and logically combining the auxiliary string with the first string to generate a corresponding output string. A least significant bit of the auxiliary string is independent from the bits of the first string, and any other bit of the auxiliary string. The method is particularly convenient for generating an overflow flag when the number to be output exceeds the representation interval. An overflow flag is generated by logically combining the most significant bits of the first and auxiliary strings.
Bibliography:Application Number: US20030651075