ESD protection circuit with high substrate-triggering efficiency

An ESD protection circuit with high substrate-triggering efficiency. The circuit comprises a multi-finger-type device having a plurality of finger gates below which a parasitic BJT is formed, a plurality of finger sources, each of which is an emitter of one parasitic BJT, and at least one finger dra...

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Bibliographic Details
Main Authors HSU KUOUN, KER MING-DOU
Format Patent
LanguageEnglish
Published 18.03.2004
Edition7
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:An ESD protection circuit with high substrate-triggering efficiency. The circuit comprises a multi-finger-type device having a plurality of finger gates below which a parasitic BJT is formed, a plurality of finger sources, each of which is an emitter of one parasitic BJT, and at least one finger drain coupled to a pad, a plurality of voltage drop elements, each of which is coupled between one of the finger sources and a power line to detect a transient current flowing through one of the finger gates, and a plurality of feedback circuits, each of which is coupled between a base and an emitter respectively of a first and second parasitic BJT, and activates the first BJT to bypass ESD current during an ESD event.
Bibliography:Application Number: US20030653303