Tri-layer masking architecture for patterning dual damascene interconnects

This invention relates to a method of dual damascene integration for manufacture of integrating circuits using three top hard mask layers having alternating etch selectivity characteristics.

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Bibliographic Details
Main Authors WAETERLOOS JOOST J. M, TOWNSEND PAUL H, MILLS LYNNE K, STRITTMATTER RICHARD J
Format Patent
LanguageEnglish
Published 27.11.2003
Edition7
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:This invention relates to a method of dual damascene integration for manufacture of integrating circuits using three top hard mask layers having alternating etch selectivity characteristics.
Bibliography:Application Number: US20030402073