Sub-milliohm on-chip interconnection

• Main Authors: KELLER MICHAEL, STELLBERGER ACHIM, JORGER WOLFGANG
• Format: Patent
• Language: English
• Published: 09.10.2003
• Edition: 7
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

A method to form a very low resistivity interconnection in the manufacture of an integrated circuit device is achieved. A bottom conductive layer is formed overlying a substrate. The bottom conductive layer creates a first electrical coupling of a first location and a second location of the integrated circuit device. A dielectric layer is formed overlying the bottom conductive layer. A top conductive layer is formed overlying the dielectric layer. The top conductive layer is coupled to the bottom conductive layer through openings in the dielectric layer to form a second electrical coupling of the first location and the second location. A metal wire is bonded to the top conductive layer to form a third electrical coupling of the first location and the second location to complete the very low resistivity interconnection in the manufacture of the integrated circuit device.