Configuration of multi-cluster processor from single wide thread to two half-width threads

The invention provides a processor that processes bundles of instructions preferentially through clusters or execution units according to thread characteristics. The cluster architectures of the invention preferably include capability to process "multi-threaded" instructions. Selectively,...

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Bibliographic Details
Main Author DELANO ERIC
Format Patent
LanguageEnglish
Published 28.08.2003
Edition7
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:The invention provides a processor that processes bundles of instructions preferentially through clusters or execution units according to thread characteristics. The cluster architectures of the invention preferably include capability to process "multi-threaded" instructions. Selectively, the architecture either (a) processes singly-threaded instructions through a single cluster to avoid bypassing and to increase throughput, or (b) processes singly-threaded instructions through multiple processes to increase "per thread" performance. The architecture may be "configurable" to operate in one of two modes: in a "wide" mode of operation, the processor's internal clusters collectively process bundled instructions of one thread of a program at the same time; in a "throughput" mode of operation, those clusters independently process instruction bundles of separate program threads. Clusters are often implemented on a common die, with a core and register file per cluster.
Bibliography:Application Number: US20020083872