Semiconductor device and manufacturing method thereof

A high performance super-minituarized double gate SOIMOS being fabricated by re-distributing the impurity with high concentration at the interface of a buried gate insulative film and by aligning the double gate in a self-aligned manner and furthermore, by isolating completely the buried gate electr...

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Bibliographic Details
Main Authors HORIUCHI MASATADA, TAKAHAMA TAKASHI
Format Patent
LanguageEnglish
Published 19.06.2003
Edition7
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:A high performance super-minituarized double gate SOIMOS being fabricated by re-distributing the impurity with high concentration at the interface of a buried gate insulative film and by aligning the double gate in a self-aligned manner and furthermore, by isolating completely the buried gate electrodes electrically from each other, in which a multi-layered SOI substrate having an amorphous or polycrystal semiconductor layer constituted by way of a buried gate insulative film to a lower portion of an SOI layer is used, ion implantation is applied to the semiconductor layer in a pattern opposite to the upper gate electrode and the buried gate is constituted in a self-alignment relation with the upper gate.
Bibliography:Application Number: US20020299793