MEMORY CACHE BANK PREDICTION

A memory cache bank prediction unit is provided for use in a processor having a plurality of memory cache banks. The memory cache bank prediction unit has an input port that receives an instruction. The memory cache bank prediction unit also has an evaluation unit, coupled to the input port, that pr...

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Bibliographic Details
Main Authors RAPPOPORT LIHU, YOAZ ADI, RONEN RONNY, VALENTINE BOB, EREZ MATTAN, JOURDAN STEPHEN J
Format Patent
LanguageEnglish
Published 13.03.2003
Edition7
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:A memory cache bank prediction unit is provided for use in a processor having a plurality of memory cache banks. The memory cache bank prediction unit has an input port that receives an instruction. The memory cache bank prediction unit also has an evaluation unit, coupled to the input port, that predicts which of the plurality of memory cache banks is associated with the instruction.
Bibliography:Application Number: US19990474381