Semiconductor chip package and method of fabricating same
A semiconductor chip package and a method of fabricating a semiconductor chip package provide a reduced chip size package. The semiconductor chip package includes a semiconductor chip; a plurality of pads disposed on an upper surface of the semiconductor chip; a thermosetting resin formed on the upp...
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Main Author | |
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Format | Patent |
Language | English |
Published |
09.01.2003
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Edition | 7 |
Subjects | |
Online Access | Get full text |
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Summary: | A semiconductor chip package and a method of fabricating a semiconductor chip package provide a reduced chip size package. The semiconductor chip package includes a semiconductor chip; a plurality of pads disposed on an upper surface of the semiconductor chip; a thermosetting resin formed on the upper surface of the semiconductor chip such that through-holes in the thermosetting resin expose the pads; a multi-layer wiring pattern formed on the thermosetting resin; a connecting unit electrically connecting the multi-layer wiring pattern with the pads; a solder resist on the thermosetting resin, the multi-layer wiring pattern and the connecting unit, such that at least one through-hole in the solder resist exposes a portion of the multi-layer wiring pattern; and a solder ball mounted on the through-hole of the solder resist in contact with the exposed portion of the metal pattern. |
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Bibliography: | Application Number: US20020232652 |