BURN-IN METHOD AND BURN-IN DEVICE

To provide a burn-in method and device capable of accelerating burn-in also in a peripheral circuit portion and a logic circuit portion as well as a memory cell array portion. A high temperature stress is applied to a wafer to be an evaluation object (Step SP11). Next, a low temperature stress and a...

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Bibliographic Details
Main Author YAMAMOTO SHIGEHISA
Format Patent
LanguageEnglish
Published 04.04.2002
Edition7
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
INFORMATION STORAGE
MEASURING
MEASURING ELECTRIC VARIABLES
MEASURING MAGNETIC VARIABLES
PHYSICS
SEMICONDUCTOR DEVICES
STATIC STORES
TESTING
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Summary:To provide a burn-in method and device capable of accelerating burn-in also in a peripheral circuit portion and a logic circuit portion as well as a memory cell array portion. A high temperature stress is applied to a wafer to be an evaluation object (Step SP11). Next, a low temperature stress and an electric stress are applied to the wafer (Step SP12). Then, it is decided whether a predetermined stress is applied to the wafer or not (Step SP13). If a result of the decision at the Step SP13 is "YES", it is decided whether a defective portion is generated in each chip of the wafer or not (Step SP14). Referring to a chip decided to have a failure generated thereon as a result of the decision at the Step SP14, it is decided whether repair is executed for the defective portion or not (Step SP15). If a result of the decision at the Step SP15 is "YES", the repair is executed for the defective portion (Step SP16).
Bibliography:Application Number: US20010813801