New poly spacer split gate cell with extremely small cell size
A dual-gate cell structure with self-aligned gates. A polysilicon spacer forms a second gate (213) separated from a first gate (201), which is also polysilicon, by a dielectric layer (207). A drain region (219) and a source region (221) are formed next to the gates within a shallower well. The shall...
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Main Author | |
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Format | Patent |
Language | English |
Published |
09.08.2001
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Edition | 7 |
Subjects | |
Online Access | Get full text |
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Summary: | A dual-gate cell structure with self-aligned gates. A polysilicon spacer forms a second gate (213) separated from a first gate (201), which is also polysilicon, by a dielectric layer (207). A drain region (219) and a source region (221) are formed next to the gates within a shallower well. The shallower well is positioned above a deep well region. In one embodiment, the second gate (213) acts as a floating gate in a flash cell. The floating gate may be programmed and erased by the application of appropriate voltage levels to the first gate (201), source (221), and/or drain (219). The self-aligned nature of the second gate (213) to the first gate (201) allows a very small dual-gate cell to be formed. |
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Bibliography: | Application Number: US20010822563 |