Block-to-block isolation and deep contact using pillars in a memory array

• Main Authors: Gowda, Srivardhan, Parat, Krishna, Cleereman, Brian J, Thimmegowda, Deepak, Liu, Liu, Sel, Jong Sun, Lin, Jui-Yen, Zhou, Baosuo
• Format: Patent
• Language: English
• Published: 15.10.2024
• Subjects: ELECTRICITY; INFORMATION STORAGE; PHYSICS; STATIC STORES

An integrated circuit memory includes a first memory block and an adjacent second memory block. The first memory block comprises a first memory pillar around which a first memory cell is formed. The second memory block comprises a second memory pillar around which a second memory cell is formed. An isolation or slit area between the first and second memory blocks electrically isolates the first and second memory blocks. In an example, the slit area comprising a slit pillar around which no memory cells are formed. The slit pillar is a dummy pillar, and insulator material electrically isolates the slit pillar from a Word Line (WL) through which it passes. The isolation layer electrically can also isolate a (WL) of the first memory block from a corresponding WL of the second memory block. In an example, the slit pillar and the memory pillars have at least in part similar structures.