Router architecture for multi-dimensional topologies in on-chip and on-package networks

A router may include input buffers that receive a packet being transmitted from a source to a destination, a state generator that determines a state for the packet, and a memory representing weights for actions corresponding to possible states. The memory may be configured to return an action corres...

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Bibliographic Details
Main Authors Zaman, Naveed, Suri, Tameesh, Sheikh, Bilal Shafi, Shak, Myron
Format Patent
LanguageEnglish
Published 17.09.2024
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC COMMUNICATION TECHNIQUE
ELECTRIC DIGITAL DATA PROCESSING
ELECTRICITY
PHYSICS
TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION
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Summary:A router may include input buffers that receive a packet being transmitted from a source to a destination, a state generator that determines a state for the packet, and a memory representing weights for actions corresponding to possible states. The memory may be configured to return an action corresponding to the state of the packet, where the action may indicate a next hop in the route between the source and the destination. The router may also include reward logic configured to generate the weights for the plurality of actions in the memory. The reward logic may receive a global reward corresponding to the route between the source and the destination, calculate a local reward corresponding to next hops available to the router; and combine the global reward and the local reward to generate the weights for the plurality of actions in the memory.
Bibliography:Application Number: US202117348183