Predicated compare-exchange-shuffle instruction for parallel processor

A processor-implemented method for executing a hardware intrinsic programming instruction, includes performing one or more Boolean operations in combination with one or more permutation operations in response to the hardware intrinsic programming instruction being a single predicated compare-exchang...

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Bibliographic Details
Main Authors Aswani, Himanshu Pradeep, Ramteke, Mithil, Patchala, Venkata Prema Sai Sravan, Kandimalla, Sridhar
Format Patent
LanguageEnglish
Published 03.09.2024
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:A processor-implemented method for executing a hardware intrinsic programming instruction, includes performing one or more Boolean operations in combination with one or more permutation operations in response to the hardware intrinsic programming instruction being a single predicated compare-exchange-shuffle programming instruction. The method also includes outputting a sub-sorted list after the performing of the one or more Boolean operation in combination with the one or more permutation operation.
Bibliography:Application Number: US202318189115