Memory array circuit and method of manufacturing same
A memory array includes a first memory cell configured to store data, a second memory cell configured to store data and a bit line extending along the first direction, and being over the first memory cell and the second memory cell. The first memory cell and the second memory cell are arranged along...
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Main Authors | , , , , , |
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Format | Patent |
Language | English |
Published |
27.08.2024
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Subjects | |
Online Access | Get full text |
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Abstract | A memory array includes a first memory cell configured to store data, a second memory cell configured to store data and a bit line extending along the first direction, and being over the first memory cell and the second memory cell. The first memory cell and the second memory cell are arranged along a first direction in a first column of memory cells. The bit line includes a first conductor extending in the first direction and being in a first conductive layer, and a second conductor extending in the first direction and being in a second conductive layer different from the first conductive layer. |
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AbstractList | A memory array includes a first memory cell configured to store data, a second memory cell configured to store data and a bit line extending along the first direction, and being over the first memory cell and the second memory cell. The first memory cell and the second memory cell are arranged along a first direction in a first column of memory cells. The bit line includes a first conductor extending in the first direction and being in a first conductive layer, and a second conductor extending in the first direction and being in a second conductive layer different from the first conductive layer. |
Author | Pan, Hsien-Yu Chen, Yen-Huei Lin, Chih-Yu Liao, Hung-Jen Fujiwara, Hidehiro Singh, Sahil Preet |
Author_xml | – fullname: Fujiwara, Hidehiro – fullname: Lin, Chih-Yu – fullname: Singh, Sahil Preet – fullname: Chen, Yen-Huei – fullname: Liao, Hung-Jen – fullname: Pan, Hsien-Yu |
BookMark | eNrjYmDJy89L5WQw9U3NzS-qVEgsKkqsVEjOLEouzSxRSMxLUchNLcnIT1HIT1PITcwrTUtMLiktysxLVyhOzE3lYWBNS8wpTuWF0twMim6uIc4euqkF-fGpxQWJyal5qSXxocGGRgbmJoamZk5GxsSoAQBqkC8Q |
ContentType | Patent |
DBID | EVB |
DatabaseName | esp@cenet |
DatabaseTitleList | |
Database_xml | – sequence: 1 dbid: EVB name: esp@cenet url: http://worldwide.espacenet.com/singleLineSearch?locale=en_EP sourceTypes: Open Access Repository |
DeliveryMethod | fulltext_linktorsrc |
Discipline | Medicine Chemistry Sciences Physics |
ExternalDocumentID | US12074156B2 |
GroupedDBID | EVB |
ID | FETCH-epo_espacenet_US12074156B23 |
IEDL.DBID | EVB |
IngestDate | Fri Sep 06 06:14:19 EDT 2024 |
IsOpenAccess | true |
IsPeerReviewed | false |
IsScholarly | false |
Language | English |
LinkModel | DirectLink |
MergedId | FETCHMERGED-epo_espacenet_US12074156B23 |
Notes | Application Number: US202117213074 |
OpenAccessLink | https://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20240827&DB=EPODOC&CC=US&NR=12074156B2 |
ParticipantIDs | epo_espacenet_US12074156B2 |
PublicationCentury | 2000 |
PublicationDate | 20240827 |
PublicationDateYYYYMMDD | 2024-08-27 |
PublicationDate_xml | – month: 08 year: 2024 text: 20240827 day: 27 |
PublicationDecade | 2020 |
PublicationYear | 2024 |
RelatedCompanies | TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD |
RelatedCompanies_xml | – name: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD |
Score | 3.5578206 |
Snippet | A memory array includes a first memory cell configured to store data, a second memory cell configured to store data and a bit line extending along the first... |
SourceID | epo |
SourceType | Open Access Repository |
SubjectTerms | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY INFORMATION STORAGE PHYSICS SEMICONDUCTOR DEVICES STATIC STORES |
Title | Memory array circuit and method of manufacturing same |
URI | https://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20240827&DB=EPODOC&locale=&CC=US&NR=12074156B2 |
hasFullText | 1 |
inHoldings | 1 |
isFullTextHit | |
isPrint | |
link | http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwfV1bS8MwFD6MeX3Tqei8EEH6Vly7ps0eitAbQ9gFt8neRpo2MGHZaDtk_94kbs4XfU0gnATO-XKS830H4MmiHcq5zaWLu9h0JOCaxMm4SVKl90kxJh1FFO713e7EeZ3iaQ0-dlwYrRP6qcURpUcx6e-Vjter_SNWpGsry-d0LoeWL8nYj4xtdqz0umzPiAI_Hg6iQWiEoT8ZGf0337I1drqBDNcH6hqtdPbj90CxUla_ISU5g8OhXE1U51DLRQNOwl3ntQYc97Yf3g040hWarJSDWy8sLwD3VHnsBtGioBvE5gVbzytERYa--0GjJUcLKtaKtKBZiKiki_wSHpN4HHZNacnsZ9uzyWhvdPsK6mIp8mtAFmtl2JYh1mOukxEv9VLCOi3MuUz2CM1uoPn3Os3_Jm_hVB2hejG1vTuoV8U6v5eQW6UP-qy-ACS0hRY |
link.rule.ids | 230,309,786,891,25594,76906 |
linkProvider | European Patent Office |
linkToHtml | http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwfV3fT8IwEL4Q_IFvOjWKv2pi9rYIY93Gw2LCBpnKBhFmeCNdtyaYMMg2YvjvbSuIL_raJs21yd3Xa-_7DuChSdqEMZ1xFzexZnDA1WwjYZodC71PgrHdFkThIDT9yHiZ4EkFPrZcGKkT-inFEblHUe7vpYzXy90jlidrK4vHeMaHFk-9seOpm-xY6HXplup1nO5w4A1c1XWdaKSGb05Tl9hpdni43rOEOq-4Or13BCtl-RtSesewP-SrZeUJVNJMgZq77bymwGGw-fBW4EBWaNKCD268sDgFHIjy2DUieU7WiM5yupqViGQJ-u4HjRYMzUm2EqQFyUJEBZmnZ3Df645dX-OWTH-2PY1GO6Nb51DNFll6AahJGwnWeYi1qGkkthVbsU3bDcwYT_ZsklxC_e916v9N3kHNHwf9af85fL2CI3Gc4vVUt66hWuar9IbDbxnfynP7AoZDiAM |
openUrl | ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Apatent&rft.title=Memory+array+circuit+and+method+of+manufacturing+same&rft.inventor=Fujiwara%2C+Hidehiro&rft.inventor=Lin%2C+Chih-Yu&rft.inventor=Singh%2C+Sahil+Preet&rft.inventor=Chen%2C+Yen-Huei&rft.inventor=Liao%2C+Hung-Jen&rft.inventor=Pan%2C+Hsien-Yu&rft.date=2024-08-27&rft.externalDBID=B2&rft.externalDocID=US12074156B2 |