Memory device that includes a duty correction circuit, memory controller that includes a duty sensing circuit, and storage device that includes a memory device

A storage device includes a plurality of memory chips and a chip. The plurality of memory chips includes a first memory chip configured to generate a first signal based on a first clock signal, and a second memory chip configured to generate a second signal based on a second clock signal. The chip i...

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Bibliographic Details
Main Authors Lee, Junha, Kim, Tongsung, Yang, Manjae, Jo, Youngmin, Jeong, Byunghoon, Yoon, Chiweon
Format Patent
LanguageEnglish
Published 27.08.2024
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:A storage device includes a plurality of memory chips and a chip. The plurality of memory chips includes a first memory chip configured to generate a first signal based on a first clock signal, and a second memory chip configured to generate a second signal based on a second clock signal. The chip is configured to receive the first and second signals and generate and output a first and second comparison signal based on a duty cycle of the first and second signals. The first memory chip is further configured to generate a first corrected signal by adjusting a duty cycle of the first clock signal based on the first comparison signal, and the second memory chip is further configured to generate a second corrected signal by adjusting a duty cycle of the second clock signal based on the second comparison signal.
Bibliography:Application Number: US202117404510