Minimization of silicon germanium facets in planar metal oxide semiconductor structures

• Main Authors: Chou, Jing-Jyu, Cheng, Shan-Yun, Kao, Ching-Hung, Wang, Yi-Sin, Chen, Yi-Ting
• Format: Patent
• Language: English
• Published: 06.08.2024
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

A method and apparatus for minimizing silicon germanium facets in planar metal oxide semiconductor structures is disclosed. For example, a device fabricated according to the method may include a semiconductor substrate, a plurality of gate stacks formed on the substrate, a plurality of source/drain regions formed from silicon germanium, and a shallow trench isolation region positioned between two source/drain regions of the plurality of source/drain regions. Each source/drain region of the plurality of source/drain regions is positioned adjacent to at least one gate stack of the plurality of gate stacks. Moreover, the shallow trench isolation region forms a trench in the substrate without intersecting the two source/drain regions.