Stacked transistors
A first interconnect layer is bonded to a first substrate. The first interconnect layer is deposited on a first device layer on a second device layer on a second substrate. The second device layer is revealed from the second substrate side. A first insulating layer is deposited on the revealed secon...
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Main Authors | , , |
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Format | Patent |
Language | English |
Published |
06.08.2024
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Subjects | |
Online Access | Get full text |
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Summary: | A first interconnect layer is bonded to a first substrate. The first interconnect layer is deposited on a first device layer on a second device layer on a second substrate. The second device layer is revealed from the second substrate side. A first insulating layer is deposited on the revealed second device layer. A first opening is formed in the first insulating layer to expose a first portion of the second device layer. A contact region is formed on the exposed first portion of the second device layer. |
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Bibliography: | Application Number: US202217567753 |