Device layout design for improving device performance

The present disclosure relates an integrated chip. The integrated chip includes an isolation region disposed within a substrate and surrounding an active area. A gate structure is disposed over the substrate and has a base region and a gate extension finger protruding outward from a sidewall of the...

Full description

Saved in:
Bibliographic Details
Main Authors Tsai, Chun-Lin, Chang, Shih-Pang, Wu, Haw-Yun, Chang, Yao-Chung
Format Patent
LanguageEnglish
Published 23.07.2024
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
Online AccessGet full text

Cover

More Information
Summary:The present disclosure relates an integrated chip. The integrated chip includes an isolation region disposed within a substrate and surrounding an active area. A gate structure is disposed over the substrate and has a base region and a gate extension finger protruding outward from a sidewall of the base region along a first direction to past opposing sides of the active area. A source contact is disposed within the active area and a drain contact is disposed within the active area and is separated from the source contact by the gate extension finger. A first plurality of conductive contacts are arranged on the gate structure and separated along the first direction. The first plurality of conductive contacts are separated by distances overlying the gate extension finger.
Bibliography:Application Number: US202217672325