Management of error-handling flows in memory devices using probability data structure

Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including running sample data through each of a set of error-handling operations performed on data residing in a segment of the m...

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Bibliographic Details
Main Authors Thiruvengadam, Aswin, Rayaprolu, Vamsi Pavan
Format Patent
LanguageEnglish
Published 09.07.2024
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including running sample data through each of a set of error-handling operations performed on data residing in a segment of the memory device in an existing order associated with a workload; obtaining error recovery data as a result of running the sample data; and determining an optimized order of the set of error-handling operations based on probability of error recovery and latency data, wherein the probability of error recovery is based on the error recovery data, and wherein the optimized order comprises an adjustment to an order of one or more error-handling operations of the set of error-handling operations in the existing order.
Bibliography:Application Number: US202217943082