Methods of forming stacked integrated circuits using selective thermal atomic layer deposition on conductive contacts and structures formed using the same

Methods of bonding and structures with such bonding are disclosed. One such method includes providing a first substrate with a first electrical contact; providing a second substrate with a second electrical contact above the first electrical contact, wherein an upper surface of the first electrical...

Full description

Saved in:
Bibliographic Details
Main Authors Li, Ming-Jui, Bakir, Muhannad, Breeden, Mike, Kummel, Andrew, Hollin, Jonathan, Linn, Nyi Myat Khine, Wang, Victor, Winter, Charles H
Format Patent
LanguageEnglish
Published 02.07.2024
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
Online AccessGet full text

Cover

More Information
Summary:Methods of bonding and structures with such bonding are disclosed. One such method includes providing a first substrate with a first electrical contact; providing a second substrate with a second electrical contact above the first electrical contact, wherein an upper surface of the first electrical contact is spaced apart from a lower surface of the second electrical contact by a gap; and depositing a layer of selective metal on the lower surface of the second electrical contact and on the upper surface of the first electrical contact by a thermal Atomic Layer Deposition (ALD) process until the gap is filled to create a bond between the first electrical contact and the second electrical contact.
Bibliography:Application Number: US202117470630