Integrated circuit and method of forming same and a system

A multi-bit flip-flop includes a first flip-flop, a second flip-flop and a first inverter. The first flip-flop has a first driving capability, and includes a first reset pin configured to receive a first reset signal. The second flip-flop has a second driving capability different from the first driv...

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Bibliographic Details
Main Authors Chen, Sheng-Hsiung, Chen, Wen-Hao, Wang, Shao-Huan, Ou, Hung-Chih, Ku, Chun-Yao
Format Patent
LanguageEnglish
Published 18.06.2024
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:A multi-bit flip-flop includes a first flip-flop, a second flip-flop and a first inverter. The first flip-flop has a first driving capability, and includes a first reset pin configured to receive a first reset signal. The second flip-flop has a second driving capability different from the first driving capability. The second flip-flop includes a second reset pin configured to receive the first reset signal, and the first reset pin and the second reset pin are coupled together. The first inverter is configured to receive a first clock signal on a first clock pin, and configured to generate a second clock signal inverted from the first clock signal. The first flip-flop and the second flip-flop are configured to share at least the first clock pin.
Bibliography:Application Number: US202318337245