Memory device performing temperature compensation and operating method thereof

A memory device is provided. The memory device includes: a memory cell array including a plurality of memory cells; a page buffer circuit connected to the memory cell array through a plurality of bit lines and including a page buffer connected to each of the plurality of bit lines, the page buffer i...

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Bibliographic Details
Main Authors Kim, Minhwi, Park, Ilhan, Kang, Kyoman, Chun, Jinyoung, Cho, Yongsung
Format Patent
LanguageEnglish
Published 04.06.2024
Subjects
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:A memory device is provided. The memory device includes: a memory cell array including a plurality of memory cells; a page buffer circuit connected to the memory cell array through a plurality of bit lines and including a page buffer connected to each of the plurality of bit lines, the page buffer including at least one first latch for storing data based on a voltage level of a first sensing node; and a control circuit configured to adjust a level of a voltage signal provided to the page buffer circuit. The page buffer includes a trip control transistor arranged between the at least one first latch and the first sensing node, and wherein the control circuit is further configured to, based on a read operation being performed on the memory cell array, control a trip control voltage to be provided to a gate of the trip control transistor. A level of the trip control voltage varies according to a temperature of the memory device.
Bibliography:Application Number: US202217710283