Semiconductor structure, method for fabricating thereof, and method for fabricating semiconductor layout

A semiconductor structure, including a plurality of connection patterns disposed on the substrate, and a merged pattern disposed between adjacent two of the connection patterns, wherein the merged pattern includes a first outer line, a central line and a second outer line sequentially arranged along...

Full description

Saved in:
Bibliographic Details
Main Authors Tung, Yu-Cheng, Fang, Xiaopei, Jhan, Yi-Wang, Yan, Yifei, Lin, Gang-Yi
Format Patent
LanguageEnglish
Published 28.05.2024
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
Online AccessGet full text

Cover

More Information
Summary:A semiconductor structure, including a plurality of connection patterns disposed on the substrate, and a merged pattern disposed between adjacent two of the connection patterns, wherein the merged pattern includes a first outer line, a central line and a second outer line sequentially arranged along a first direction and connected with each other, and an end surface of the first outer line, an end surface of the central line and an end surface of the second outer line are misaligned along the first direction.
Bibliography:Application Number: US202217706613