Processing unit with fast read speed memory device

A memory cell includes a first resistive memory element, a second resistive memory element electrically coupled with the first resistive memory element at a common node, and a switching element comprising an input terminal electrically coupled with the common node, the switching element comprising a...

Full description

Saved in:
Bibliographic Details
Main Authors Ware, Frederick A, Bronner, Gary Bela, Sekar, Deepak Chandra
Format Patent
LanguageEnglish
Published 14.05.2024
Subjects
INFORMATION STORAGE
PHYSICS
STATIC STORES
Online AccessGet full text

Cover

More Information
Summary:A memory cell includes a first resistive memory element, a second resistive memory element electrically coupled with the first resistive memory element at a common node, and a switching element comprising an input terminal electrically coupled with the common node, the switching element comprising a driver configured to float during one or more operations.
Bibliography:Application Number: US202217665123